isp1583 NXP Semiconductors, isp1583 Datasheet - Page 49

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1583_6
Product data sheet
Table 51.
Code
00h
01h
02h to 05h
06h
07h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
DMA commands
Name
GDMA Read
GDMA Write
-
MDMA Read
MDMA Write
Read 1F0
Poll BSY
Read Task Files
-
Validate Buffer
Clear Buffer
Restart
Reset DMA
MDMA stop
Rev. 06 — 20 August 2007
Description
Generic DMA IN token transfer (slave mode only): Data is
transferred from the external DMA bus to the internal buffer.
Strobe: DIOW by external DMA controller.
Generic DMA OUT token transfer (slave mode only): Data is
transferred from the internal buffer to the external DMA bus.
Strobe: DIOR by external DMA controller.
reserved
Multi-word DMA Read: Data is transferred from the external
DMA bus to the internal buffer.
Multi-word DMA Write: Data is transferred from the internal
buffer to the external DMA bus.
Read at address 1F0h: Initiates a PIO Read cycle from Task
File 1F0. Before issuing this command, the task file byte count
must be programmed at address 1F4h (LSByte) and 1F5h
(MSByte).
Poll BSY status bit for ATAPI device: Starts repeated PIO
Read commands to poll the BSY status bit of the ATAPI device.
When BSY = 0, polling is terminated and an interrupt is
generated. The interrupt can be masked but the interrupt bit will
still be set. Therefore, you can manually poll this interrupt bit.
Read Task Files: Reads all task files. When Task File Index is
set to logic 0, this command reads all registers, except 1F0h and
1F7h. If Task File Index is not logic 0, the Task register of the
address set in the Task File register will be read. When the
reading is completed, an interrupt is generated. The interrupt
can be masked off, however, the interrupt bit will still be set.
Therefore, you can manually poll this interrupt bit.
reserved
Validate Buffer (for debugging only): Request from the
microcontroller to validate the endpoint buffer, following an
ATA-to-USB data transfer.
Clear Buffer: Request from the microcontroller to clear the
endpoint buffer, after a DMA-to-USB data transfer. Logic 1 clears
the TX buffer of the indexed endpoint; the RX buffer is not
affected. The TX buffer is automatically cleared once data is
sent on the USB bus. This bit is set only when it is necessary to
forcefully clear the buffer.
Remark: If using double buffer, to clear both the buffers issue
the Clear Buffer command two times, that is, set and clear this
bit two times.
Restart: Request from the microcontroller to move the buffer
pointers to the beginning of the endpoint FIFO.
Reset DMA: Initializes the DMA core to its power-on reset state.
Remark: When the DMA core is reset during the Reset DMA
command, the DREQ, DACK, DIOW and DIOR handshake pins
will temporarily be asserted. This can confuse the external DMA
controller. To prevent this, start the external DMA controller only
after the DMA reset.
MDMA stop: This command immediately stops the MDMA data
transfer. This is applicable for commands 06h and 07h only.
Hi-Speed USB Peripheral Controller
© NXP B.V. 2007. All rights reserved.
ISP1583
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