isp1583 NXP Semiconductors, isp1583 Datasheet - Page 17

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 3.
ISP1583_6
Product data sheet
Pin
BUS_CONF/
DA0
LOW
HIGH
Bus configuration modes
PIO width
AD[7:0]
A[7:0] and
D[15:0]
7.10 Reconfiguring endpoints
7.11 System controller
7.12 Modes of operation
The ISP1583 endpoints have a limitation when implementing a composite device with at
least two functionalities that require the support of alternate settings, for example, the
video class and audio class devices. The ISP1583 endpoints cannot be reconfigured on
the fly because it is implemented as a FIFO base. The internal RAM partition will be
corrupted if there is a need to reconfigure endpoints on the fly because of alternate
settings request, causing data corruption.
For details and work-around, refer to
(AN10046)”.
The system controller implements the USB power-down capabilities of the ISP1583.
Registers are protected against data corruption during wake-up following a resume (from
the suspend state) by locking the write access, until an unlock code is written to the
Unlock Device register (see
The ISP1583 has two bus configuration modes, selected using pin BUS_CONF/DA0 at
power-up:
Details of bus configurations for each mode are given in
for each mode are given in
1. Assign a value to the DMA Endpoint register. It can be any value other than the value
2. Assign Endpoint Index register = 2h
3. Assign Control Function register = 10h
4. Assign Endpoint Index register = 2h
5. Assign Control Function register = 10h
•
•
assigned to the Endpoint Index register. In this example, do not assign 2h to the DMA
Endpoint register. See remark in
Split bus mode (BUS_CONF/DA0 = LOW): 8-bit multiplexed address and data bus,
and separate 8-bit or 16-bit DMA bus
Generic processor mode (BUS_CONF/DA0 = HIGH): separate 8-bit address and
16-bit data bus
DMA width
WIDTH = 0
D[7:0]
D[7:0]
WIDTH = 1
D[15:0]
D[15:0]
Rev. 06 — 20 August 2007
Section
Table 88
Description
split bus mode:
generic processor mode:
•
•
•
•
13.
Multiplexed address and data on pins AD[7:0]
Separate 8-bit or 16-bit DMA bus on pins DATA[15:0]
Separate 8-bit address on pins AD[7:0]
16-bit data (PIO and DMA) on pins DATA[15:0]
Section
Ref. 3 “ISP1581/2/3 Frequently Asked Questions
and
Table
8.3.1.
89).
Hi-Speed USB Peripheral Controller
Table
3. Typical interface circuits
© NXP B.V. 2007. All rights reserved.
ISP1583
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