isp1583 NXP Semiconductors, isp1583 Datasheet - Page 39

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 32.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Endpoint Index register: bit allocation
8.3.1 Endpoint Index register (address: 2Ch)
8.3 Data flow registers
7
-
-
-
reserved
Table 31.
The Endpoint Index register selects a target endpoint for register access by the
microcontroller. The register consists of 1 byte, and the bit allocation is shown in
The following registers are indexed:
For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the
Endpoint Index register must first be written with 02h.
Remark: The Endpoint Index register and the DMA Endpoint register must not point to the
same endpoint, irrespective of IN and OUT.
Remark: The delay time from the Write Endpoint Index register to the Read Data Port
register must be at least 190 ns.
Remark: The delay time from the Write Endpoint Index register to the Write Data Port
register must be at least 100 ns.
Bit
7
6
5
4
3
2
1
0
•
•
•
•
•
•
Buffer length
Buffer status
Control function
Data port
Endpoint MaxPacketSize
Endpoint type
6
-
-
-
Interrupt Enable register: bit description
Symbol
IEVBUS
IEDMA
IEHS_STA
IERESM
IESUSP
IEPSOF
IESOF
IEBRST
EP0SETUP
R/W
5
0
0
Rev. 06 — 20 August 2007
Description
Logic 1 enables interrupt for V
Logic 1 enables interrupt on DMA Interrupt Reason register change
detection.
Logic 1 enables interrupt on detecting a high-speed status change.
Logic 1 enables interrupt on detecting a resume state.
Logic 1 enables interrupt on detecting a suspend state.
Logic 1 enables interrupt on detecting a pseudo SOF.
Logic 1 enables interrupt on detecting an SOF.
Logic 1 enables interrupt on detecting a bus reset.
R/W
4
0
0
R/W
3
0
0
ENDPIDX[3:0]
…continued
Hi-Speed USB Peripheral Controller
BUS
sensing.
R/W
2
0
0
R/W
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
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