isp1583 NXP Semiconductors, isp1583 Datasheet - Page 61

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
EP6TX
EP2TX
VBUS
R/W
R/W
R/W
23
15
0
0
0
0
7
0
0
Table 81.
Bit
31 to 26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
EP6RX
EP2RX
DMA
R/W
R/W
R/W
22
14
0
0
0
0
6
0
0
Interrupt register: bit description
Symbol
-
EP7TX
EP7RX
EP6TX
EP6RX
EP5TX
EP5RX
EP4TX
EP4RX
EP3TX
EP3RX
EP2TX
EP2RX
EP1TX
EP1RX
EP0TX
EP0RX
-
EP0SETUP
VBUS
DMA
HS_STAT
HS_STAT
EP5TX
EP1TX
R/W
R/W
R/W
21
13
0
0
0
0
5
0
0
Rev. 06 — 20 August 2007
Description
reserved
logic 1 indicates the endpoint 7 TX buffer as interrupt source
logic 1 indicates the endpoint 7 RX buffer as interrupt source
logic 1 indicates the endpoint 6 TX buffer as interrupt source
logic 1 indicates the endpoint 6 RX buffer as interrupt source
logic 1 indicates the endpoint 5 TX buffer as interrupt source
logic 1 indicates the endpoint 5 RX buffer as interrupt source
logic 1 indicates the endpoint 4 TX buffer as interrupt source
logic 1 indicates the endpoint 4 RX buffer as interrupt source
logic 1 indicates the endpoint 3 TX buffer as interrupt source
logic 1 indicates the endpoint 3 RX buffer as interrupt source
logic 1 indicates the endpoint 2 TX buffer as interrupt source
logic 1 indicates the endpoint 2 RX buffer as interrupt source
logic 1 indicates the endpoint 1 TX buffer as interrupt source
logic 1 indicates the endpoint 1 RX buffer as interrupt source
logic 1 indicates the endpoint 0 data TX buffer as interrupt source
logic 1 indicates the endpoint 0 data RX buffer as interrupt source
reserved
logic 1 indicates that a SETUP token was received on endpoint 0
logic 1 indicates a transition from LOW to HIGH on V
DMA status: Logic 1 indicates a change in the DMA Interrupt Reason
register.
High speed status: Logic 1 indicates a change from full-speed to
high-speed mode (HS connection). This bit is not set, when the system
goes into full-speed suspend.
RESUME
EP5RX
EP1RX
R/W
R/W
R/W
20
12
0
0
0
0
4
0
0
EP4TX
EP0TX
SUSP
R/W
R/W
R/W
19
11
0
0
0
0
3
0
0
Hi-Speed USB Peripheral Controller
EP4RX
EP0RX
PSOF
R/W
R/W
R/W
18
10
0
0
0
0
2
0
0
reserved
EP3TX
SOF
R/W
R/W
17
9
0
0
1
0
0
-
-
-
© NXP B.V. 2007. All rights reserved.
BUS
ISP1583
EP0SETUP
BRESET
EP3RX
R/W
R/W
R/W
61 of 100
16
8
0
0
0
0
0
0
1