isp1583 NXP Semiconductors, isp1583 Datasheet - Page 23

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1583_6
Product data sheet
7.16 Power-on reset
The ISP1583 requires a minimum pulse width of 500 s.
The RESET_N pin can either be connected to V
externally controlled (by the microcontroller, ASIC, and so on). When V
connected to the RESET_N pin, the internal pulse width t
The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5
on the V
t0 — The internal POR starts with a HIGH level.
t1 — The detector will see the passing of the trip level and a delay element will add
another t
t2 to t3 — The internal POR pulse will be generated whenever V
for more than 11 s.
t4 to t5 — The dip is too short (< 11 s) and the internal POR pulse will not react and will
remain LOW.
Figure 11
Fig 10. POR timing
Fig 11. Clock with respect to the external POR
t0
CC(POR)
(1) PORP = Power-On Reset Pulse.
Power on V
Stable external clock is to be available at B.
The ISP1583 is operational at C.
PORP
shows the availability of the clock with respect to the external POR.
t1
RESET_N
before it drops to LOW.
V
t
PORP
external
CC(3V3)
curve
clock
CC(3V3)
Rev. 06 — 20 August 2007
(Figure
at A.
10).
A
500 s
t2
B
2 ms
t3
CC(3V3)
t
PORP
Hi-Speed USB Peripheral Controller
(using the internal POR circuit) or
PORP
t4
C
will typically be 200 ns.
t5
CC(POR)
004aaa906
CC(3V3)
© NXP B.V. 2007. All rights reserved.
ISP1583
drops below V
004aaa389
PORP
V
V
BAT(POR)
is directly
trip
(1)
23 of 100
trip