isp1583 NXP Semiconductors, isp1583 Datasheet - Page 57

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 70.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Interrupt Reason register: bit allocation
TEST3
15
R
0
0
7
-
-
-
Table 71.
Bit
15
14 to 13
12
11
10
9
8
7 to 5
4
3
2
1
0
reserved
14
6
-
-
-
-
-
-
Symbol
TEST3
-
GDMA_STOP
EXT_EOT
INT_EOT
INTRQ_
PENDING
DMA_XFER_OK
-
READ_1F0
BSY_DONE
TF_RD_DONE
CMD_INTRQ_OK
-
reserved
DMA Interrupt Reason register: bit description
13
5
-
-
-
-
-
-
Rev. 06 — 20 August 2007
READ_1F0
Description
This bit is set when a DMA transfer for a packet (OUT transfer)
terminates before the whole packet is transferred. This bit is a
status bit, and the corresponding mask bit of this register is always
0. Writing any value other than 0 has no effect.
reserved
GDMA Stop: When the GDMA_STOP command is issued to DMA
Command registers, it means the DMA transfer has successfully
terminated.
External EOT: Logic 1 indicates that an external EOT is detected.
This is applicable only in GDMA slave mode.
Internal EOT: Logic 1 indicates that an internal EOT is detected;
see
Interrupt Pending: Logic 1 indicates that a pending interrupt was
detected on pin INTRQ.
DMA Transfer OK: Logic 1 indicates that the DMA transfer is
completed (DMA Transfer Counter has become zero). This bit is
only used in GDMA (slave) mode and MDMA (master) mode.
reserved
Read 1F0: Logic 1 indicates that the 1F0 FIFO contains unread
data and the microcontroller can start reading data.
Busy Done: Logic 1 indicates that the BSY status bit has become
zero and polling has been stopped.
Task File Read Done: Logic 1 indicates that the Read Task Files
command has been completed.
Command Interrupt OK: Logic 1 indicates that all bytes from the
FIFO have been transferred (DMA Transfer Count zero) and an
interrupt on pin INTRQ was detected.
reserved
GDMA_
STOP
R/W
R/W
12
Table
0
0
4
0
0
72.
EXT_EOT
DONE
BSY_
R/W
R/W
11
0
0
3
0
0
Hi-Speed USB Peripheral Controller
INT_EOT
TF_RD_
DONE
R/W
R/W
10
0
0
2
0
0
INTRQ_OK
PENDING
INTRQ_
CMD_
R/W
R/W
9
0
0
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
XFER_OK
reserved
DMA_
R/W
57 of 100
8
0
0
0
-
-
-