isp1583 NXP Semiconductors, isp1583 Datasheet - Page 35

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 25.
Table 28.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Interrupt Configuration register: bit allocation
OTG register: bit allocation
8.2.4 OTG register (address: 12h)
R/W
CDBGMOD[1:0]
7
1
1
7
-
-
-
reserved
Table 26.
Table 27.
[1]
The bit allocation of the OTG register is given in
Bit
7 to 6
5 to 4
3 to 2
1
0
Value
00h
01h
1Xh
First NAK: the first NAK on an IN or OUT token is generated after a set-up token and an ACK sequence.
R/W
6
1
1
6
-
-
-
Symbol
CDBGMOD[1:0]
DDBGMODIN[1:0]
DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see
INTLVL
INTPOL
CDBGMOD
interrupt on all ACK and
NAK
interrupt on all ACK
interrupt on all ACK and
first NAK
Interrupt Configuration register: bit description
Debug mode settings
[1]
R/W
DDBGMODIN[1:0]
R/W
DP
5
0
0
5
1
1
Rev. 06 — 20 August 2007
BSESSVALID
Description
Control Endpoint 0 Debug Mode: For values, see
Data Debug Mode IN: For values, see
Interrupt Level: Selects signaling mode on output INT (0 = level;
1 = pulsed). In pulsed mode, an interrupt produces a 60 ns pulse.
Interrupt Polarity: Selects signal polarity on output INT (0 =
active LOW, 1 = active HIGH).
R/W
R/W
4
1
1
4
-
-
DDBGMODIN
interrupt on all ACK and
NAK
interrupt on ACK
interrupt on all ACK and
first NAK
INITCOND
DDBGMODOUT[1:0]
[1]
R/W
3
1
1
R/W
3
-
-
Table
Hi-Speed USB Peripheral Controller
28.
DISCV
R/W
R/W
2
1
1
2
0
0
DDBGMODOUT
interrupt on all ACK, NYET
and NAK
interrupt on ACK and NYET
interrupt on all ACK, NYET
and first NAK
Table 27
unchanged
INTLVL
Table 27
R/W
R/W
VP
1
0
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
[1]
Table 27
unchanged
INTPOL
OTG
R/W
R/W
35 of 100
0
0
0
0
0