isp1583 NXP Semiconductors, isp1583 Datasheet - Page 15

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1583_6
Product data sheet
7.6.1 NXP Parallel Interface Engine (PIE)
7.6.2 Peripheral circuit
7.6.3 HS detection
7.5 OTG SRP module
7.6 NXP high-speed transceiver
When pin BUS_CONF/DA0 = HIGH, the microcontroller interface switches to generic
processor mode in which AD[7:0] is the 8-bit address bus and DATA[15:0] is the separate
16-bit data bus. If pin BUS_CONF/DA0 = LOW, the interface is in split bus mode, where
AD[7:0] is the local microprocessor bus (multiplexed address and data) and DATA[15:0] is
solely used as the DMA bus.
When pin MODE0/DA1 = HIGH, pins RW_N/RD_N and DS_N/WR_N are the read and
write strobes (8051 mode). If pin MODE0/DA1 = LOW, pins RW_N/RD_N and
DS_N/WR_N represent the direction and data strobes (Freescale mode).
When pin MODE1 = LOW, pin ALE/A0 is used to latch the multiplexed address on pins
AD[7:0]. When pin MODE1 = HIGH, pin ALE/A0 is used to indicate address or data. Pin
MODE1 is only used in split bus mode; in generic processor mode, it must be tied to
V
The microcontroller handler allows the external microcontroller to access the register set
in the NXP SIE, as well as the DMA handler. The initialization of the DMA configuration is
done through the microcontroller handler.
The OTG supplement defines a Session Request Protocol (SRP), which allows a B-device
to request the A-device to turn on V
A-device, which may be battery-powered, to conserve power by turning off V
there is no bus activity while still providing a means for the B-device to initiate bus activity.
Any A-device, including a PC or laptop, can respond to SRP. Any B-device, including a
standard USB peripheral, can initiate SRP.
The ISP1583 is a device that can initiate SRP.
In the High-Speed (HS) transceiver, the NXP PIE interface uses a 16-bit parallel
bidirectional data interface. The functions of the HS module also include bit-stuffing or
de-stuffing and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic.
To maintain a constant current driver for HS transmit circuits and to bias other analog
circuits, an internal band gap reference circuit and an RREF resistor form the reference
current. This circuit requires an external precision resistor (12.0 k
the analog ground.
The ISP1583 handles more than one electrical state, Full-Speed (FS) or High-Speed
(HS), under the USB specification. When the USB cable is connected from the peripheral
to the Host Controller, the ISP1583 defaults to the FS state, until it sees a bus reset from
the Host Controller.
CC(I/O)
.
Rev. 06 — 20 August 2007
BUS
and start a session. This protocol allows the
Hi-Speed USB Peripheral Controller
1 %) connected to
© NXP B.V. 2007. All rights reserved.
ISP1583
BUS
when
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