isp1583 NXP Semiconductors, isp1583 Datasheet - Page 56

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 66.
CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = LOW.
Table 67.
CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = HIGH.
[1]
Table 68.
CS1_N = LOW, CS0_N = HIGH, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = LOW.
Table 69.
CS1_N = LOW, CS0_N = HIGH, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = HIGH.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Task File register 1F7 is a write-only register; a read will return FFh.
Task File 1F6 register (address: 4Dh): bit allocation
Task File 1F7 register (address: 44h): bit allocation
Task File 3F6 register (address: 4Eh): bit allocation
Task File 3F7 register (address: 4Fh): bit allocation
8.4.6 DMA Interrupt Reason register (address: 50h)
R/W
R/W
R/W
W
7
0
0
7
0
0
7
0
0
7
0
0
This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a
DMA command is executed. An interrupt source is cleared by writing logic 1 to the
corresponding bit. On detecting the interrupt, the external microprocessor must read the
DMA Interrupt Reason register and mask it with the corresponding bits in the DMA
Interrupt Enable register to determine the source of the interrupt.
The bit allocation is given in
R/W
R/W
R/W
W
6
0
0
6
0
0
6
0
0
6
0
0
command (ATA) or status
R/W
R/W
R/W
drive/head/LBA[27:24] (ATA) or drive (ATAPI)
W
5
0
0
5
0
0
5
0
0
5
0
0
alternate status/command (ATA or ATAPI)
drive address (ATA) or reserved (ATAPI)
Rev. 06 — 20 August 2007
Table
R/W
R/W
R/W
W
4
0
0
4
0
0
4
0
0
4
0
0
70.
[1]
/command (ATAPI)
R/W
R/W
R/W
W
3
0
0
3
0
0
3
0
0
3
0
0
Hi-Speed USB Peripheral Controller
R/W
R/W
R/W
W
2
0
0
2
0
0
2
0
0
2
0
0
R/W
R/W
R/W
W
1
0
0
1
0
0
1
0
0
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
R/W
R/W
R/W
56 of 100
W
0
0
0
0
0
0
0
0
0
0
0
0