isp1583 NXP Semiconductors, isp1583 Datasheet - Page 97

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 78. DMA Burst Counter register: bit allocation . . .60
Table 79. DMA Burst Counter register: bit description . .60
Table 80. Interrupt register: bit allocation . . . . . . . . . . . .60
Table 81. Interrupt register: bit description . . . . . . . . . . .61
Table 82. Chip ID register: bit allocation . . . . . . . . . . . . .62
Table 83. Chip ID register: bit description . . . . . . . . . . . .62
Table 84. Frame Number register: bit allocation . . . . . . .63
Table 85. Frame Number register: bit description . . . . . .63
Table 86. Scratch register: bit allocation . . . . . . . . . . . . .63
Table 87. Scratch register: bit description . . . . . . . . . . . .63
Table 88. Unlock Device register: bit allocation . . . . . . . .64
Table 89. Unlock Device register: bit description . . . . . . .64
Table 90. Test Mode register: bit allocation . . . . . . . . . . .64
Table 91. Test Mode register: bit description . . . . . . . . . .65
Table 92. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 93. Recommended operating conditions . . . . . . . .66
Table 94. Static characteristics: supply pins . . . . . . . . . .66
Table 95. Static characteristics: digital pins . . . . . . . . . . .67
Table 96. Static characteristics: OTG detection . . . . . . .67
Table 97. Static characteristics: analog I/O pins DP
Table 98. Dynamic characteristics . . . . . . . . . . . . . . . . . .68
Table 99. Dynamic characteristics: analog I/O pins
Table 100.ISP1583 register access timing parameters:
Table 101.ISP1583 register access timing parameters:
Table 102.ISP1583 register access timing parameters:
Table 103.ISP1583 register access timing parameters:
Table 104.ISP1583 register access timing parameters:
Table 105.ISP1583 register access timing parameters:
Table 106.PIO mode timing parameters . . . . . . . . . . . . . .80
Table 107.GDMA slave mode timing parameters . . . . . . .82
Table 108.MDMA mode timing parameters . . . . . . . . . . .84
Table 109.SnPb eutectic process (from J-STD-020C) . . .91
Table 110.Lead-free process (from J-STD-020C) . . . . . .91
Table 111.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table 112.Revision history . . . . . . . . . . . . . . . . . . . . . . . .94
ISP1583_6
Product data sheet
and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .68
separate address and data buses . . . . . . . . . .70
separate address and data buses . . . . . . . . . .72
multiplexed address/data bus . . . . . . . . . . . . .74
multiplexed address/data bus . . . . . . . . . . . . .75
multiplexed address/data bus . . . . . . . . . . . . .76
multiplexed address/data bus . . . . . . . . . . . . .77
Rev. 06 — 20 August 2007
Hi-Speed USB Peripheral Controller
© NXP B.V. 2007. All rights reserved.
ISP1583
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