isp1583 NXP Semiconductors, isp1583 Datasheet - Page 50

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 52.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
DMA Transfer Counter register: bit allocation
8.4.2 DMA Transfer Counter register (address: 34h)
R/W
31
23
0
0
Table 51.
This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates
the remaining number of bytes left for transfer. The bit allocation is given in
For IN endpoint — Because there is a FIFO in the ISP1583 DMA controller, some data
may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and
the maximum delay time for data to be shifted to endpoint buffer is 60 ns.
For OUT endpoint — Data will not be cleared from the endpoint buffer, until all the data is
read from the DMA FIFO.
If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover when
it reaches zero.
Code
13h
14h to 20h
21h
22h
23h
24h
25h
26h
27h
28h
29h to FFh
R/W
30
22
0
0
DMA commands
Name
GDMA stop
-
Read Task File
register 1F1h
Read Task File
register 1F2h
Read Task File
register 1F3h
Read Task File
register 1F4h
Read Task File
register 1F5h
Read Task File
register 1F6h
Read Task File
register 3F6h
Read Task File
register 3F7h
-
R/W
29
21
0
0
Rev. 06 — 20 August 2007
…continued
DMACR4 = DMACR[31:24]
DMACR3 = DMACR[23:16]
Description
GDMA stop: This command stops the GDMA data transfer. Any
data in the OUT endpoint that is not transferred by the DMA will
remain in the buffer. The FIFO data for the IN endpoint will be
written to the endpoint buffer. An interrupt bit will be set to
indicate the completion of the DMA Stop command.
reserved
Read Task File register 1F1h: When reading is completed, an
interrupt is generated.
Read Task File register 1F2h: When reading is completed, an
interrupt is generated.
Read Task File register 1F3h: When reading is completed, an
interrupt is generated.
Read Task File register 1F4h: When reading is completed, an
interrupt is generated.
Read Task File register 1F5h: When reading is completed, an
interrupt is generated.
Read Task File register 1F6h: When reading is completed, an
interrupt is generated.
Read Task File register 3F6h: When reading is completed, an
interrupt is generated.
Read Task File register 3F7h: When reading is completed, an
interrupt is generated.
reserved
R/W
28
20
0
0
R/W
27
19
0
0
Hi-Speed USB Peripheral Controller
R/W
26
18
0
0
R/W
25
17
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
Table
52.
R/W
50 of 100
24
16
0
0