isp1583 NXP Semiconductors, isp1583 Datasheet - Page 64

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 88.
Table 90.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Unlock Device register: bit allocation
Test Mode register: bit allocation
8.5.5 Unlock Device register (address: 7Ch)
8.5.6 Test Mode register (address: 84h)
unchanged
FORCEHS
15
W
W
7
R/W
7
0
To protect registers from getting corrupted when the ISP1583 goes into suspend, the write
operation is disabled if bit PWRON in the Mode register is set to logic 0. In this case, when
the chip resumes, the Unlock Device command must first be issued to this register before
attempting to write to the rest of the registers. This is done by writing unlock code (AA37h)
to this register. The bit allocation of the Unlock Device register is given in
Table 89.
When bit PWRON in the Mode register is logic 1, the chip is powered. In such a case, you
do not need to issue the Unlock command because the microprocessor is powered and
therefore, the RW_N/RD_N, DS_N/WR_N and CS_N signals maintain their states.
When bit PWRON is logic 0, the RW_N/RD_N, DS_N/WR_N and CS_N signals are
floating because the microprocessor is not powered. To protect the ISP1583 registers
from being corrupted during suspend, register write is locked when the chip goes into
suspend. Therefore, you need to issue the Unlock command to unlock the ISP1583
registers.
This 1-byte register allows the firmware to set the DP and DM pins to predetermined
states for testing purposes. The bit allocation is given in
Remark: Only one bit can be set at a time. Either bit FORCEHS or FORCEFS must be set
to logic 1 at a time. Of the four bits PRBS, KSTATE, JSTATE and SE0_NAK only one bit
must be set at a time. This must be implemented for the Hi-Speed USB logo compliance
testing. To exit test mode, power cycle is required.
Bit
15 to 0
14
W
W
6
6
-
-
-
Unlock Device register: bit description
reserved
Symbol
ULCODE[15:0]
13
W
W
5
5
-
-
-
Rev. 06 — 20 August 2007
Description
Unlock Code: Writing data AA37h unlocks internal registers and
FIFOs for writing, following a resume.
unchanged
ULCODE[15:8] = AAh
FORCEFS
ULCODE[7:0] = 37h
12
W
W
R/W
4
not applicable
not applicable
not applicable
not applicable
4
0
PRBS
11
W
W
R/W
3
3
0
0
Hi-Speed USB Peripheral Controller
KSTATE
Table
R/W
10
W
W
2
2
0
0
90.
JSTATE
R/W
W
W
9
1
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
Table
SE0_NAK
88.
R/W
64 of 100
W
W
8
0
0
0
0