isp1583 NXP Semiconductors, isp1583 Datasheet - Page 53

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 56.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
DMA Hardware register: bit allocation
R/W
7
0
0
ENDIAN[1:0]
This register determines the polarity of bus control signals (EOT, DACK, DREQ, DIOR and
DIOW) and DMA mode (master or slave). It also controls whether the upper and lower
parts of the data bus are swapped (bits ENDIAN[1:0]), for modes GDMA (slave) and
MDMA (master) only.
Table 57.
Bit
7 to 6
5
4
3
2
1
0
R/W
6
0
0
Symbol
ENDIAN[1:0] Endian: These bits determine whether the data bus is swapped between
EOT_POL
MASTER
ACK_POL
DREQ_POL
WRITE_POL Write Polarity: Selects the DIOW strobe polarity.
READ_POL
DMA Hardware register: bit description
EOT_POL
R/W
5
0
0
Description
the internal RAM and the DMA bus. This only applies for modes GDMA
(slave) and MDMA (master).
00 — Normal data representation; 16-bit bus: MSByte on DATA[15:8] and
LSByte on DATA[7:0].
01 — Swapped data representation; 16-bit bus: MSByte on DATA[7:0] and
LSByte on DATA[15:8].
10 — reserved
11 — reserved
Remark: While operating with the 8-bit data bus, bits ENDIAN[1:0] must
always be set to logic 00.
EOT Polarity: Selects the polarity of the End-Of-Transfer input; used in
GDMA slave mode only.
0 — EOT is active LOW
1 — EOT is active HIGH
Master or Slave Selection: Selects DMA master or slave mode.
0 — GDMA slave mode
1 — MDMA master mode
Acknowledgment Polarity: Selects the DMA acknowledgment polarity.
0 — DACK is active LOW
1 — DACK is active HIGH
DREQ Polarity: Selects the DMA request polarity.
0 — DREQ is active LOW
1 — DREQ is active HIGH
0 — DIOW is active LOW
1 — DIOW is active HIGH
Read Polarity: Selects the DIOR strobe polarity.
0 — DIOR is active LOW
1 — DIOR is active HIGH
Rev. 06 — 20 August 2007
MASTER
R/W
4
0
0
ACK_POL
R/W
3
0
0
Hi-Speed USB Peripheral Controller
DREQ_
POL
R/W
2
1
1
WRITE_
POL
R/W
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
READ_
POL
R/W
53 of 100
0
0
0