isp1583 NXP Semiconductors, isp1583 Datasheet - Page 32

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 20.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Address register: bit allocation
8.2.1 Address register (address: 00h)
8.2.2 Mode register (address: 0Ch)
unchanged
8.2 Initialization registers
DEVEN
R/W
7
0
Remark: Write zero to all reserved bits, unless otherwise specified.
This register sets the USB assigned address and enables the USB device.
shows the Address register bit allocation.
Bits DEVADDR will be cleared whenever a bus reset, a power-on reset or a soft reset
occurs. Bit DEVEN will be cleared whenever a power-on reset or a soft reset occurs.
In response to standard USB request SET_ADDRESS, the firmware must write the
(enabled) device address to the Address register, followed by sending an empty packet to
the host. The new device address is activated when the device receives an
acknowledgment from the host for the empty packet token.
Table 21.
This register consists of 2 bytes (bit allocation: see
The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft
reset, clock signals and SoftConnect operation.
Bit
7
6 to 0
•
•
•
•
•
•
Buffer Length
Buffer Status
Control Function
Data Port
Endpoint MaxPacketSize
Endpoint Type
R/W
6
0
0
Symbol
DEVEN
DEVADDR[6:0] Device Address: This field specifies the USB device address.
Address register: bit description
R/W
5
0
0
Rev. 06 — 20 August 2007
Description
Device Enable: Logic 1 enables the device. The device will not
respond to the host, unless this bit is set.
R/W
4
0
0
DEVADDR[6:0]
R/W
3
0
0
Hi-Speed USB Peripheral Controller
Table
R/W
22).
2
0
0
R/W
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
Table 20
R/W
32 of 100
0
0
0