isp1583 NXP Semiconductors, isp1583 Datasheet - Page 58

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 73.
Table 74.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Interrupt Enable register: bit allocation
DMA Endpoint register: bit allocation
8.4.7 DMA Interrupt Enable register (address: 54h)
8.4.8 DMA Endpoint register (address: 58h)
TEST4
15
R
0
0
7
7
-
-
-
-
-
-
Table 72.
This 2-byte register controls the interrupt generation of the source bits in the DMA
Interrupt Reason register (see
description is given in
Logic 1 enables the interrupt generation. After a bus reset, interrupt generation is
disabled, with values turning to logic 0.
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in
INT_EOT
1
1
0
reserved
14
6
6
-
-
-
-
-
-
-
-
-
reserved
reserved
Internal EOT-functional relation with DMA_XFER_OK bit
DMA_XFER_OK
0
1
1
13
5
5
-
-
-
-
-
-
-
-
-
Table
Rev. 06 — 20 August 2007
IE_GDMA_
READ_1F0
71.
Description
During the DMA transfer, there is a premature termination with
short packet.
DMA transfer is completed with short packet and the DMA
transfer counter has reached 0.
DMA transfer is completed without any short packet and the DMA
transfer counter has reached 0.
STOP
Table
R/W
R/W
IE_
12
0
0
4
0
0
4
-
-
-
70). The bit allocation is given in
Table
IE_BSY_
IE_EXT_
DONE
EOT
R/W
R/W
R/W
74.
11
0
0
3
0
0
3
0
0
Hi-Speed USB Peripheral Controller
EPIDX[2:0]
RD_DONE
IE_INT_
IE_TF_
EOT
R/W
R/W
R/W
10
0
0
2
0
0
2
0
0
IE_INTRQ_
INTRQ_OK
PENDING
IE_CMD_
R/W
R/W
R/W
Table
9
0
0
1
0
0
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
73. The bit
XFER_OK
IE_DMA_
reserved
DMADIR
R/W
R/W
58 of 100
8
0
0
0
0
0
0
-
-
-