isp1583 NXP Semiconductors, isp1583 Datasheet - Page 51

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 54.
ISP1583_6
Product data sheet
Bit
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Configuration register: bit allocation
XFER_CNT
8.4.3 DMA Configuration register (address: 38h)
DIS_
R/W
15
7
0
0
R/W
R/W
R/W
-
-
-
23
15
0
0
0
0
7
0
0
reserved
Table 53.
This register defines the DMA configuration for GDMA mode. The DMA Configuration
register consists of 2 bytes. The bit allocation is given in
Bit
31 to 24
23 to 16
15 to 8
7 to 0
R/W
R/W
R/W
14
6
22
14
-
-
-
-
-
-
0
0
0
0
6
0
0
DMA Transfer Counter register: bit description
Symbol
DMACR4 = DMACR[31:24]
DMACR3 = DMACR[23:16]
DMACR2 = DMACR[15:8]
DMACR1 = DMACR[7:0]
reserved
MODE
ATA_
R/W
R/W
R/W
R/W
13
21
13
0
0
5
-
-
-
0
0
0
0
5
0
0
Rev. 06 — 20 August 2007
DMACR2 = DMACR[15:8]
DMACR1 = DMACR[7:0]
R/W
R/W
R/W
R/W
DMA_MODE[1:0]
12
20
12
0
0
4
0
0
0
0
4
0
0
-
-
-
Description
DMA transfer counter byte 4 (MSByte)
DMA transfer counter byte 3
DMA transfer counter byte 2
DMA transfer counter byte 1 (LSByte)
R/W
R/W
R/W
R/W
R/W
19
11
11
0
0
0
0
3
0
0
0
0
3
0
0
MODE[1:0]
Hi-Speed USB Peripheral Controller
Table
R/W
R/W
R/W
R/W
R/W
18
10
10
0
0
0
0
2
0
0
0
0
2
0
0
54.
PIO_MODE[2:0]
reserved
R/W
R/W
R/W
R/W
17
0
0
9
0
0
1
0
0
© NXP B.V. 2007. All rights reserved.
9
0
0
1
-
-
-
ISP1583
WIDTH
R/W
R/W
R/W
R/W
R/W
51 of 100
16
0
0
8
0
0
0
0
0
0
0
1
1
8
0