isp1583 NXP Semiconductors, isp1583 Datasheet - Page 81

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1583_6
Product data sheet
Fig 31. PIO mode timing
(1) The device address consists of signals CS1_N, CS0_N, DA2, DA1 and DA0.
(2) The data bus width depends on the PIO access command used. The Task File register access uses 8 bits (DATA[7:0]),
(3) The device can negate READY/IORDY to extend the PIO cycle with wait states. The host determines whether or not to
(4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals.
(write) DATA [ 7:0 ]
(read) DATA [ 7:0 ]
READY/IORDY
READY/IORDY
READY/IORDY
DIOR, DIOW
except for Task File register 1F0 that uses 16 bits (DATA[15:0]). DMA commands 04h and 05h also use a 16-bit data bus.
extend the current cycle after t
a) Device keeps READY/IORDY released (high-impedance): no wait state is generated.
b) Device negates READY/IORDY during t
c) Device negates READY/IORDY during t
state is generated. The cycle is completed as soon as READY/IORDY is re-asserted. For extended read cycles (DIOR
asserted), the read data on lines DATAn must be valid at t
device
address
valid
(3a)
(3b)
(3c)
(1)
(4)
(2)
(2)
HIGH
su4
t
su1
, following the assertion of DIOR or DIOW. The following three cases are distinguished:
su4
su4
, but re-asserts READY/IORDY before t
and keeps READY/IORDY negated for at least 5 ns after t
Rev. 06 — 20 August 2007
t
t
su4
su4
T
cy1
d1
before READY/IORDY is asserted.
t
w1
t
w3
Hi-Speed USB Peripheral Controller
su4
t
t
su5
su2
t
su3
expires: no wait state is generated.
t
t
h3(min)
h2
t
h1
t
su4
d2
t
w2
© NXP B.V. 2007. All rights reserved.
expires: a wait
ISP1583
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