isp1583 NXP Semiconductors, isp1583 Datasheet - Page 48

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 49.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
DMA Command register: bit allocation
8.4.1 DMA Command register (address: 30h)
W
7
1
1
Table 47.
Table 48.
Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the
other control signals are not 3-stated.
The DMA Command register is a 1-byte register (for bit allocation, see
initiates all DMA transfer activity on the DMA controller. The register is write-only: reading
it will return FFh.
Remark: The DMA bus will be in 3-state, until a DMA command is executed.
Table 50.
Control bits
DMA Hardware register
ENDIAN[1:0]
EOT_POL
MASTER
ACK_POL,
DREQ_POL,
WRITE_POL,
READ_POL
Control bits
DMA Configuration register
ATA_MODE
DMA_MODE[1:0]
PIO_MODE[2:0]
DMA Hardware register
MASTER
Bit
7 to 0
W
6
1
1
Control bits for Generic DMA transfers
Control bits for IDE-specified DMA transfers
DMA Command register: bit description
Symbol
DMA_CMD[7:0]
Description
GDMA read/write (opcode =
00h/01h)
determines whether data is to
be byte swapped or normal;
applicable only in 16-bit mode
selects polarity of the EOT
signal
set to logic 0 (slave)
selects polarity of DMA
handshake signals
W
Description
MDMA read/write (opcode = 06h/07h)
set to logic 1 (ATA transfer)
selects MDMA mode; timing are ATA(PI) compatible
selects PIO mode; timing are ATA(PI) compatible
set to logic 0
5
1
1
Rev. 06 — 20 August 2007
Description
DMA command code, see
PIO Read or Write that started using DMA Command register
only performs a 16-bit transfer.
DMA_CMD[7:0]
W
4
1
1
W
3
1
1
MDMA (master) read/write
(opcode = 06h/07h)
determines whether data is to
be byte swapped or normal;
applicable only in 16-bit mode
input EOT is not used
set to logic 1 (master)
selects polarity of DMA
handshake signals
…continued
Hi-Speed USB Peripheral Controller
Table
W
2
1
1
51.
W
1
1
1
Table
© NXP B.V. 2007. All rights reserved.
ISP1583
Reference
Table 54
Table 56
Reference
Table 56
49) that
48 of 100
W
0
1
1