isp1583 NXP Semiconductors, isp1583 Datasheet - Page 14

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1583_6
Product data sheet
7.1 DMA interface, DMA handler and DMA registers
7.2 Hi-Speed USB transceiver
7.3 MMU and integrated RAM
7.4 Microcontroller interface and microcontroller handler
The ISP1583 operates on a 12 MHz crystal oscillator. An integrated 40
multiplier generates the internal sampling clock of 480 MHz.
The DMA block can be subdivided into two blocks: DMA handler and DMA interface.
The firmware writes to the DMA Command register to start a DMA transfer (see
The command opcode determines whether a generic DMA, Parallel I/O (PIO) or
Multi-word DMA (MDMA) transfer will start. The handler interfaces to the same FIFO
(internal RAM) as used by the USB core. On receiving the DMA command, the DMA
handler directs the data from the endpoint FIFO to the external DMA device or from the
external DMA device to the endpoint FIFO.
The DMA interface configures the timing and the DMA handshake. Data can be
transferred using either the DIOR and DIOW strobes or the DACK and DREQ
handshakes. DMA configurations are set up by writing to the DMA Configuration register
(see
For an IDE-based storage interface, applicable DMA modes are PIO and MDMA
(Multi-word DMA; ATA).
For a generic DMA interface, DMA modes that can be used are Generic DMA (GDMA)
slave.
Remark: The DMA endpoint buffer length must be a multiple of 4 bytes.
For details on DMA registers, see
The analog transceiver directly interfaces to the USB cable through integrated termination
resistors. The high-speed transceiver requires an external resistor (12.0 k
between pin RREF and ground to ensure an accurate current mirror that generates the
Hi-Speed USB current drive. A full-speed transceiver is integrated as well. This makes the
ISP1583 compliant to Hi-Speed USB and Original USB, supporting both the high-speed
and full-speed physical layers. After automatic speed detection, the NXP Serial Interface
Engine (SIE) sets the transceiver to use either high-speed or full-speed signaling.
The Memory Management Unit (MMU) manages the access to the integrated RAM that is
shared by the USB, microcontroller handler and DMA handler. Data from the USB bus is
stored in the integrated RAM, which is cleared only when the microcontroller has read the
corresponding endpoint, or the DMA controller has written all data from the RAM of the
corresponding endpoint to the DMA bus. The OUT endpoint buffer can also be forcibly
cleared by setting bit CLBUF in the Control Function register. A total of 8 kB RAM is
available for buffering.
The microcontroller interface allows direct interfacing to most microcontrollers and
microprocessors. The interface is configured at power-up through pins BUS_CONF/DA0,
MODE1 and MODE0/DA1.
Table 54
and
Table
Rev. 06 — 20 August 2007
55).
Section
8.4.
Hi-Speed USB Peripheral Controller
© NXP B.V. 2007. All rights reserved.
ISP1583
PLL clock
1 %)
Table
14 of 100
49).