isp1583 NXP Semiconductors, isp1583 Datasheet - Page 62

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 82.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Chip ID register: bit allocation
8.5.2 Chip ID register (address: 70h)
8.5.3 Frame Number register (address: 74h)
23
15
R
R
R
0
0
1
1
7
0
0
Table 81.
This read-only register contains the chip identification and hardware version numbers.
The firmware must check this information to determine functions and features supported.
The register contains 3 bytes, and the bit allocation is shown in
Table 83.
This read-only register contains the frame number of the last successfully received
Start-Of-Frame (SOF). The register contains 2 bytes, and the bit allocation is given in
Table
Bit
4
3
2
1
0
Bit
23 to 16
15 to 8
7 to 0
84. In case of 8-bit access, the register content is returned lower byte first.
22
14
R
R
R
0
0
0
0
6
0
0
Interrupt register: bit description
Chip ID register: bit description
Symbol
RESUME
SUSP
PSOF
SOF
BRESET
Symbol
CHIPID[15:8]
CHIPID[7:0]
VERSION[7:0]
21
13
R
R
R
0
0
0
0
5
1
1
Rev. 06 — 20 August 2007
Description
Resume status: Logic 1 indicates that a status change from suspend
to resume (active) was detected.
Suspend status: Logic 1 indicates that a status change from active to
suspend was detected on the bus.
Pseudo SOF interrupt: Logic 1 indicates that a pseudo SOF or SOF
was received. Pseudo SOF is an internally generated clock signal
(full-speed: 1 ms period, high-speed: 125 s period) that is not
synchronized to the USB bus SOF or SOF.
SOF interrupt: Logic 1 indicates that a SOF or SOF was received.
Bus reset: Logic 1 indicates that a USB bus reset was detected. When
bit OTG in the OTG register is set, BRESET will not be set, instead, this
interrupt bit will report SE0 on DP and DM for 2 ms.
Description
Chip ID: lower byte (15h)
Chip ID: upper byte (82h)
Version: version number (30h)
20
12
R
R
R
1
1
0
0
4
1
1
VERSION[7:0]
CHIPID[15:8]
CHIPID[7:0]
…continued
19
11
R
R
R
0
0
0
0
3
0
0
Hi-Speed USB Peripheral Controller
18
10
R
R
R
1
1
0
0
2
0
0
Table
17
82.
R
R
R
0
0
9
1
1
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
62 of 100
16
R
R
R
1
1
8
0
0
0
0
0