isp1583 NXP Semiconductors, isp1583 Datasheet - Page 60

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 78.
Table 80.
ISP1583_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Burst Counter register: bit allocation
Interrupt register: bit allocation
8.5.1 Interrupt register (address: 18h)
R/W
8.5 General registers
15
31
7
0
0
-
-
-
-
-
-
Table 79.
The Interrupt register consists of 4 bytes. The bit allocation is given in
When a bit is set in the Interrupt register, it indicates that the hardware condition for an
interrupt has occurred. When the Interrupt register content is nonzero, the INT output will
be asserted corresponding to the Interrupt Enable register. On detecting the interrupt, the
external microprocessor must read the Interrupt register and mask it with the
corresponding bits in the Interrupt Enable register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various
bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.
The DMA controller only has one interrupt bit: the source for a DMA interrupt is shown in
the DMA Interrupt Reason register (see
Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can
be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt
Reason register, followed by writing logic 1 to the DMA bit of the Interrupt register.
Bit
15 to 13
12 to 0
reserved
R/W
14
30
6
0
0
-
-
-
-
-
-
Symbol
-
BURSTCOUNTER
[12:0]
DMA Burst Counter register: bit description
R/W
13
29
5
0
0
-
-
-
-
-
-
Rev. 06 — 20 August 2007
reserved
BURSTCOUNTER[7:0]
Description
reserved
Burst Counter: This register defines the burst length. The
counter must be programmed to be a multiple of two in 16-bit
mode. The value of the burst counter must be programmed so
that the burst counter is a factor of the buffer size.
It is used to determine the assertion and de-assertion of DREQ.
R/W
R/W
12
28
0
0
4
0
0
-
-
-
Table 70
R/W
R/W
11
27
0
0
3
0
0
-
-
-
BURSTCOUNTER[12:8]
and
Hi-Speed USB Peripheral Controller
Table
R/W
R/W
10
26
0
0
2
0
0
-
-
-
71).
EP7TX
R/W
R/W
R/W
25
9
0
0
1
1
1
Table
0
0
© NXP B.V. 2007. All rights reserved.
ISP1583
80.
EP7RX
R/W
R/W
R/W
60 of 100
24
8
0
0
0
0
0
0
0