isp1583 NXP Semiconductors, isp1583 Datasheet - Page 47

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1583_6
Product data sheet
In EOT-only mode, DIS_XFER_CNT must be set to logic 1. Although the DMA transfer
counter can still be programmed, it will not have any effect on the DMA transfer. The DMA
transfer will start once the DMA command is issued. Any of the following three ways will
terminate this DMA transfer:
There are three interrupts programmable to differentiate the method of DMA termination:
bits INT_EOT, EXT_EOT and DMA_XFER_OK in the DMA Interrupt Reason register (see
Table
MDMA (master) read/write (opcode = 06h/07h) — Generic DMA master mode.
Depending on the MODE[1:0] bits set in the DMA Configuration register, the DACK, DIOR
or DIOW signal strobes data. These signals are driven by the ISP1583.
In master mode, BURSTCOUNTER[12:0] in the DMA Burst Counter register,
DIS_XFER_CNT in the DMA Configuration register and the external EOT signal are not
applicable. The DMA transfer counter is always enabled and bit DMA_XFER_OK is set to
1 once the counter reaches 0.
MDMA read/write (opcode = 06h/07h) — Multi-word DMA mode for IDE transfers. The
specification of this mode can be obtained from
Interface Extension (ATA/ATAPI-4), ANSI INCITS 317-1998
are used as data strobes, while DREQ and DACK serve as handshake signals.
Table 47.
Control bits
DMA Configuration register
ATA_MODE
DMA_MODE[1:0]
DIS_XFER_CNT
MODE[1:0]
WIDTH
•
•
•
Detecting an external EOT
Detecting an internal EOT (short packet on an OUT token)
Issuing a GDMA stop command
72).
Control bits for Generic DMA transfers
Description
GDMA read/write (opcode =
00h/01h)
set to logic 0 (non-ATA
transfer)
-
disables use of DMA transfer
counter
determines active read/write
data strobe signals
selects DMA bus width: 8 or
16 bits
Rev. 06 — 20 August 2007
MDMA (master) read/write
(opcode = 06h/07h)
set to logic 1 (ATA transfer)
determines MDMA timing for
DIOR and DIOW strobes
disables use of DMA transfer
counter
determines active data
strobe(s)
selects DMA bus width: 8 or 16
bits
Ref. 4 “AT Attachment with Packet
Hi-Speed USB Peripheral Controller
(R2003)”. DIOR and DIOW
© NXP B.V. 2007. All rights reserved.
ISP1583
Reference
Table 54
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