isp1583 NXP Semiconductors, isp1583 Datasheet - Page 96

• Manufacturer Part Number: isp1583
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Operation truth table for OTG . . . . . . . . . . . . .26
Table 11. Operation truth table for SoftConnect . . . . . . .27
Table 12. Operation truth table for clock off during
Table 13. Operation truth table for back voltage
Table 14. Operation truth table for OTG . . . . . . . . . . . . .28
Table 15. Operation truth table for SoftConnect . . . . . . .28
Table 16. Operation truth table for clock off during
Table 17. Operation truth table for back voltage
Table 18. Operation truth table for OTG . . . . . . . . . . . . .29
Table 19. Register overview . . . . . . . . . . . . . . . . . . . . . .30
Table 20. Address register: bit allocation . . . . . . . . . . . .32
Table 21. Address register: bit description . . . . . . . . . . .32
Table 22. Mode register: bit allocation . . . . . . . . . . . . . . .33
Table 23. Mode register: bit description . . . . . . . . . . . . .33
Table 24. Status of the chip . . . . . . . . . . . . . . . . . . . . . . .34
Table 25. Interrupt Configuration register: bit allocation .35
Table 26. Interrupt Configuration register: bit description 35
Table 27. Debug mode settings . . . . . . . . . . . . . . . . . . . .35
Table 28. OTG register: bit allocation . . . . . . . . . . . . . . .35
Table 29. OTG register: bit description . . . . . . . . . . . . . .36
Table 30. Interrupt Enable register: bit allocation . . . . . .38
Table 31. Interrupt Enable register: bit description . . . . .38
Table 32. Endpoint Index register: bit allocation . . . . . . .39
Table 33. Endpoint Index register: bit description . . . . . .40
Table 34. Addressing of endpoint buffers . . . . . . . . . . . .40
Table 35. Control Function register: bit allocation . . . . . .40
Table 36. Control Function register: bit description . . . . .41
Table 37. Data Port register: bit allocation . . . . . . . . . . .42
Table 38. Data Port register: bit description . . . . . . . . . .42
Table 39. Buffer Length register: bit allocation . . . . . . . .43
Table 40. Buffer Length register: bit description . . . . . . .43
Table 41. Buffer Status register: bit allocation . . . . . . . . .44
Table 42. Buffer Status register: bit description . . . . . . . .44
ISP1583_6
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
Bus configuration modes . . . . . . . . . . . . . . . . .17
ISP1583 pin status . . . . . . . . . . . . . . . . . . . . . .18
ISP1583 output pin status . . . . . . . . . . . . . . . .18
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .24
Operation truth table for SoftConnect . . . . . . .26
Operation truth table for clock off during
suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Operation truth table for back voltage
compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Rev. 06 — 20 August 2007
Table 43. Endpoint MaxPacketSize register:
Table 44. Endpoint MaxPacketSize register:
Table 45. Endpoint Type register: bit allocation . . . . . . . 45
Table 46. Endpoint Type register: bit description . . . . . . 46
Table 47. Control bits for Generic DMA transfers . . . . . . 47
Table 48. Control bits for IDE-specified DMA transfers . . 48
Table 49. DMA Command register: bit allocation . . . . . . 48
Table 50. DMA Command register: bit description . . . . . 48
Table 51. DMA commands . . . . . . . . . . . . . . . . . . . . . . . 49
Table 52. DMA Transfer Counter register: bit allocation . 50
Table 53. DMA Transfer Counter register: bit description 51
Table 54. DMA Configuration register: bit allocation . . . . 51
Table 55. DMA Configuration register: bit description . . . 52
Table 56. DMA Hardware register: bit allocation . . . . . . . 53
Table 57. DMA Hardware register: bit description . . . . . 53
Table 58. Task File register functions . . . . . . . . . . . . . . . 54
Table 59. ATAPI peripheral register addressing . . . . . . . 54
Table 60. Task File 1F0 register (address: 40h): bit
Table 61. Task File 1F1 register (address: 48h): bit
Table 62. Task File 1F2 register (address: 49h): bit
Table 63. Task File 1F3 register (address: 4Ah): bit
Table 64. Task File 1F4 register (address: 4Bh): bit
Table 65. Task File 1F5 register (address: 4Ch): bit
Table 66. Task File 1F6 register (address: 4Dh): bit
Table 67. Task File 1F7 register (address: 44h): bit
Table 68. Task File 3F6 register (address: 4Eh): bit
Table 69. Task File 3F7 register (address: 4Fh): bit
Table 70. DMA Interrupt Reason register: bit allocation . 57
Table 71. DMA Interrupt Reason register: bit description 57
Table 72. Internal EOT-functional relation with
Table 73. DMA Interrupt Enable register: bit allocation . . 58
Table 74. DMA Endpoint register: bit allocation . . . . . . . 58
Table 75. DMA Endpoint register: bit description . . . . . . 59
Table 76. DMA Strobe Timing register: bit allocation . . . 59
Table 77. DMA Strobe Timing register: bit description . . 59
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 44
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DMA_XFER_OK bit . . . . . . . . . . . . . . . . . . . . . 58
Hi-Speed USB Peripheral Controller
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ISP1583
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