mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 80

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Operating Modes
Technical Data
80
ESTR — E Clock Stretch Enable
IVIS — Internal Visibility
Freescale Semiconductor, Inc.
MODB, MODA may be written once in Normal modes (SMODN = 1).
Write anytime in special modes (first write is ignored) – special
peripheral and reserved modes cannot be selected.
Determines if the E Clock behaves as a simple free-running clock or
as a bus control signal that is active only for external bus cycles.
ESTR is always one in expanded modes since it is required for
address and data bus de-multiplexing and must follow stretched
cycles.
0 = E never stretches (always free running).
1 = E stretches high during external access cycles and low during
non-visible internal accesses (IVIS = 0).
Normal modes: write once; Special modes: write anytime. Read
anytime.
This bit determines whether internal ADDR, DATA, R/W and LSTRB
signals can be seen on the external bus during accesses to internal
locations. In Special Narrow Mode if this bit is set and an internal
access occurs the data will appear wide on Ports A and B. This serves
the same function as the EMD bit of the non-multiplexed versions of
the HC12 and allows for emulation. Visibility is not available when the
part is operating in a single-chip mode.
Normal modes: write once; Special modes: write anytime EXCEPT
the first time. Read anytime.
For More Information On This Product,
0 = No visibility of internal bus operations on external bus.
1 = Internal bus operations are visible on external bus.
Go to: www.freescale.com
Operating Modes
MC68HC912DG128 — Rev 3.0
MOTOROLA