mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 284

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

IBCR — IIC Bus Control Register
Inter-IC Bus
Technical Data
284
RESET:
IBEN
Bit 7
0
IBIE
6
0
Read and write anytime
IBEN — IIC Bus Enable
IBIE — IIC Bus Interrupt Enable
IBC5-0
(hex)
Freescale Semiconductor, Inc.
This bit controls the software reset of the entire IIC module.
If the IIC module is enabled in the middle of a byte transfer the
interface behaves as follows: slave mode ignores the current transfer
on the bus and starts operating whenever a subsequent start
condition is detected. Master mode will not be aware that the bus is
busy, hence if a start cycle is initiated then the current bus cycle may
become corrupt. This would ultimately result in either the current bus
master or the IIC module losing arbitration, after which bus operation
would return to normal.
1B
1C
1D
1E
1F
For More Information On This Product,
0 = The module is reset and disabled. This is the power-on reset
1 = The IIC system is enabled. This bit must be set before any other
0 = Interrupts from the IIC module are disabled. Note that this does
1 = Interrupts from the IIC module are enabled. An IIC interrupt
MS/SL
5
0
situation. When low the IIC system is held in reset but registers
can still be accessed.
IBCR bits have any effect.
not clear any currently pending interrupt condition.
occurs provided the IBIF bit in the status register is also set.
SCL Divider
(clocks)
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Table 15-2. IIC Divider and SDA Hold values
128
144
160
192
240
Tx/Rx
4
0
Inter-IC Bus
SDA Hold
(clocks)
TXAK
17
25
25
33
33
3
0
RSTA
2
0
IBC5-0
(hex)
3B
3C
3D
3E
3F
MC68HC912DG128 — Rev 3.0
1
0
0
SCL Divider
(clocks)
2048
2304
2560
3072
3840
IBSWAI
Bit 0
0
MOTOROLA
SDA Hold
(clocks)
257
385
385
513
513
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