mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 231

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

PAFLG — Pulse Accumulator A Flag Register
MC68HC912DG128 — Rev 3.0
MOTOROLA
RESET:
BIT 7
0
0
6
0
0
PAOVI — Pulse Accumulator A Overflow Interrupt enable
PAI — Pulse Accumulator Input Interrupt enable
Read or write anytime. When the TFFCA bit in the TSCR register is set,
any access to the PACNT register will clear all the flags in the PAFLG
register.
PAOVF — Pulse Accumulator A Overflow Flag
PAIF — Pulse Accumulator Input edge Flag
Freescale Semiconductor, Inc.
Set when the 16-bit pulse accumulator A overflows from $FFFF to
$0000,or when 8-bit pulse accumulator 3 (PAC3) overflows from $FF
to $00.
This bit is cleared automatically by a write to the PAFLG register with
bit 1 set.
Set when the selected edge is detected at the PT7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation
mode the trailing edge of the gate signal at the PT7 input pin triggers
PAIF.
This bit is cleared by a write to the PAFLG register with bit 0 set.
Any access to the PACN3, PACN2 registers will clear all the flags in
this register when TFFCA bit in register TSCR($86) is set.
For More Information On This Product,
0 = interrupt inhibited
1 = interrupt requested if PAOVF is set
0 = interrupt inhibited
1 = interrupt requested if PAIF is set
5
0
0
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Enhanced Capture Timer
4
0
0
3
0
0
2
0
0
PAOVF
1
0
Enhanced Capture Timer
BIT 0
PAIF
0
Timer Registers
Technical Data
$00A1
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