mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 367

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

18.4.5.1 STATUS
STATUS— BDM Status Register
MC68HC912DG128 — Rev 3.0
MOTOROLA
RESET:
RESET:
1. ENBDM is set to 1 by the firmware in Special Single Chip mode.
(NOTE 1)
ENBDM
BIT 7
0
0
BDMACT
6
1
0
The STATUS register is read and written by the BDM hardware as a
result of serial data shifted in on the BKGD pin.
Read: all modes.
Write: Bits 3 through 5, and bit 7 are writable in all modes. Bit 6,
BDMACT, can only be written if bit 7 H/F in the INSTRUCTION register
is a zero. Bit 2, CLKSW, can only be written if bit 7 H/F in the
INSTRUCTION register is a one. A user would never write ones to bits
3 through 5 because these bits are only used by BDM firmware.
ENBDM — Enable BDM (permit active background debug mode)
BDMACT — Background Mode Active Status
Freescale Semiconductor, Inc.
BDMACT becomes set as active BDM mode is entered so that the
BDM firmware ROM is enabled and put into the map. BDMACT is
cleared by a carefully timed store instruction in the BDM firmware as
part of the exit sequence to return to user code and remove the BDM
memory from the map. This bit has 4 clock cycles write delay.
(1)
ENTAG
For More Information On This Product,
0 = BDM cannot be made active (hardware commands still
1 = BDM can be made active to allow firmware commands.
0 = BDM is not active. BDM ROM and registers are not in map.
1 = BDM is active and waiting for serial commands. BDM ROM and
5
0
0
allowed).
registers are in map
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Development Support
SDV
4
0
0
TRACE
3
0
0
CLKSW
2
0
0
1
0
0
-
Background Debug Mode
Development Support
BIT 0
0
0
-
Technical Data
Single Chip
& Periph
All other
Special
modes
$FF01
367