mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 281

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mc68hc912dg128

Manufacturer Part Number
mc68hc912dg128
Description
M68hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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IBAD — IIC Bus Address Register
IBFD — IIC Bus Frequency Divider Register
15.6 IIC Register Descriptions
MC68HC912DG128 — Rev 3.0
MOTOROLA
RESET:
RESET:
ADR7
Bit 7
Bit 7
0
0
0
ADR6
6
0
6
0
0
.
Read and write anytime
This register contains the address the IIC will respond to when
addressed as a slave; note that it is not the address sent on the bus
during the address transfer
ADR7–ADR1 — Slave Address
Read and write anytime
IBC5–IBC0 — IIC Bus Clock Rate 5–0
Freescale Semiconductor, Inc.
Bit 1 to bit 7 contain the specific slave address to be used by the IIC
module.
The default mode of IIC is slave mode for an address match on the
bus.
This field is used to prescale the clock for bit rate selection. The bit
clock generator is implemented as a prescaled shift register - IBC5-3
select the prescaler divider and IBC2-0 select the shift register tap
point. The IBC bits are decoded to give the Tap and Prescale values
as shown in
For More Information On This Product,
ADR5
IBC5
5
0
5
0
Go to: www.freescale.com
Table
ADR4
IBC4
4
0
4
0
Inter-IC Bus
15-1.
ADR3
IBC3
3
0
3
0
ADR2
IBC2
2
0
2
0
ADR1
IBC1
1
0
1
0
IIC Register Descriptions
Bit 0
Bit 0
IBC0
0
0
0
Technical Data
Inter-IC Bus
$00E1
$00E0
281

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