mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 268

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

SP0CR2 — SPI Control Register 2
Multiple Serial Interface
Technical Data
268
RESET:
Bit 7
0
0
6
0
0
CPOL, CPHA — SPI Clock Polarity, Clock Phase
SSOE — Slave Select Output Enable
LSBF — SPI LSB First enable
Read or write anytime.
PUPS — Pull-Up Port S Enable
RDPS — Reduce Drive of Port S
SPSWAI — Serial Interface Stop in WAIT mode
Freescale Semiconductor, Inc.
These two bits are used to specify the clock format to be used in SPI
operations. When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See
The SS output feature is enabled only in the master mode by
asserting the SSOE and DDS7.
Normally data is transferred most significant bit first.This bit does not
affect the position of the MSB and LSB in the data register. Reads and
writes of the data register will always have MSB in bit 7.
For More Information On This Product,
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
0 = No internal pull-ups on port S
1 = All port S input pins have an active pull-up device. If a pin is
0 = Port S output drivers operate normally
1 = All port S output pins have reduced drive capability for lower
0 = Serial interface clock operates normally
1 = Halt serial interface clock generation in WAIT mode
5
0
0
programmed as output, the pull-up device becomes inactive
power and less noise
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Multiple Serial Interface
4
0
0
PUPS
Figure 14-4
3
1
RDPS
2
0
and
Figure
SPSWAI
MC68HC912DG128 — Rev 3.0
1
0
14-5.
SPC0
Bit 0
0
MOTOROLA
$00D1