mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 177

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

CLKSEL — Clock Generator Clock select Register
MC68HC912DG128 — Rev 3.0
MOTOROLA
RESET:
Bit 7
0
0
BCSP
6
0
LHIE — Limp-Home Interrupt Enable
NOLHM —No Limp-Home Mode
Read and write anytime. Exceptions are listed below for each bit.
BCSP — Bus Clock Select PLL
BCSS — Bus Clock Select Slow
MCS — Module Clock Select
Freescale Semiconductor, Inc.
Forced to 0 when VDDPLL is at VSS level.
Read anytime; Normal modes: write once; Special modes: write
anytime. Forced to 1 when VDDPLL is at VSS level.
BCSP and BCSS bits determine the clock used by the main system
including the CPU and buses.
Cannot be set when PLLON = 0. In limp-home mode, the output of
BCSP is forced to 1, but the BCSP bit reads the latched value.
This bit has no effect when BCSP is set.
This bit determines the clock used by the ECT module and the baud
rate generators of the SCIs. In limp-home mode, the output of MCS is
forced to 0, but the MCS bit reads the latched value.
For More Information On This Product,
0 = Limp-Home interrupt is disabled
1 = Limp-Home interrupt is enabled
0 = Loss of reference clock forces the MCU in limp-home mode.
1 = Loss of reference clock causes standard Clock Monitor reset.
0 = SYSCLK is derived from the crystal clock or from SLWCLK.
1 = SYSCLK source is the PLL.
0 = SYSCLK is derived from the crystal clock EXTALi.
1 = SYSCLK source is the Slow clock SLWCLK.
0 = M clock is the same as PCLK.
1 = M clock is derived from Slow clock SLWCLK.
BCSS
5
0
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Clock Functions
4
0
0
3
0
0
Limp-Home and Fast STOP Recovery modes
MCS
2
0
1
0
0
Bit 0
0
0
Clock Functions
Technical Data
$003D
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