mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 270

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Multiple Serial Interface
SP0SR — SPI Status Register
Technical Data
270
RESET:
SPIF
Bit 7
0
WCOL
6
0
Read anytime. Write has no meaning or effect.
SPIF — SPI Interrupt Request
WCOL — Write Collision Status Flag
MODF — SPI Mode Error Interrupt Status Flag
Freescale Semiconductor, Inc.
SPIF is set after the eighth SCK cycle in a data transfer and it is
cleared by reading the SP0SR register (with SPIF set) followed by an
access (read or write) to the SPI data register.
The MCU write is disabled to avoid writing over the data being
transferred. No interrupt is generated because the error status flag
can be read upon completion of the transfer that was in progress at
the time of the error. Automatically cleared by a read of the SP0SR
(with WCOL set) followed by an access (read or write) to the SP0DR
register.
This bit is set automatically by SPI hardware if the MSTR control bit is
set and the slave select input pin becomes zero. This condition is not
permitted in normal operation. In the case where DDRS bit 7 is set,
the PS7 pin is a general-purpose output pin or SS output pin rather
than being dedicated as the SS input for the SPI system. In this
special case the mode fault function is inhibited and MODF remains
cleared. This flag is automatically cleared by a read of the SP0SR
(with MODF set) followed by a write to the SP0CR1 register.
For More Information On This Product,
0 = No write collision
1 = Indicates that a serial transfer was in progress when the MCU
5
0
0
tried to write new data into the SP0DR data register.
Go to: www.freescale.com
Multiple Serial Interface
MODF
4
0
3
0
0
2
0
0
MC68HC912DG128 — Rev 3.0
1
0
0
Bit 0
0
0
MOTOROLA
$00D3