mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 103

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MC68HC912DG128 — Rev 3.0
MOTOROLA
LSTRE — Low Strobe (LSTRB) Enable
RDWE — Read/Write Enable
CALE — Calibration Reference Enable
Freescale Semiconductor, Inc.
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime. This bit has no effect in single-chip modes or normal
expanded narrow mode.
LSTRB is used during external writes. After reset in normal expanded
mode, LSTRB is disabled. If needed, it should be enabled before
external writes. External reads do not normally need LSTRB because
all 16 data bits can be driven even if the MCU only needs 8 bits of
data.
In normal expanded narrow mode this pin is reset to an output driving
high allowing the pin to be an output while in and immediately after
reset.
TAGLO is a shared function of the PE3/LSTRB pin. In special
expanded modes with LSTRE set and the BDM tagging on, a zero at
the falling edge of E tags the instruction word low byte being read into
the instruction queue.
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime. This bit has no effect in single-chip modes.
R/W is used for external writes. After reset in normal expanded mode,
it is disabled. If needed it should be enabled before any external
writes.
Read and write anytime.
For More Information On This Product,
0 = PE3 is a general-purpose I/O pin.
1 = PE3 is configured as the LSTRB bus-control output, provided
0 = PE2 is a general-purpose I/O pin.
1 = PE2 is configured as the R/W pin. In single chip modes, RDWE
0 = Calibration reference is disabled and PE7 is general-purpose
1 = Calibration reference is enabled on PE7 in single chip and
the MCU is not in single chip or normal expanded narrow
modes.
has no effect and PE2 is a general-purpose I/O pin.
I/O in single chip or peripheral modes or if the NDBE bit is set.
peripheral modes or if the NDBE bit is set.
Bus Control and Input/Output
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Bus Control and Input/Output
Technical Data
Registers
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