mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 285

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MC68HC912DG128 — Rev 3.0
MOTOROLA
MS/SL — Master/Slave mode select bit
Tx/Rx — Transmit/Receive mode select bit
TXAK — Transmit Acknowledge enable
RSTA — Repeat Start
IBSWAI — IIC Stop in WAIT mode
Freescale Semiconductor, Inc.
Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a
START signal is generated on the bus, and the master mode is
selected. When this bit is changed from 1 to 0, a STOP signal is
generated and the operation mode changes from master to slave.
MS/SL is cleared without generating a STOP signal when the master
loses arbitration.
This bit selects the direction of master and slave transfers. When
addressed as a slave this bit should be set by software according to
the SRW bit in the status register. In master mode this bit should be
set according to the type of transfer required. Therefore, for address
cycles, this bit will always be high.
This bit specifies the value driven onto SDA during acknowledge
cycles for both master and slave receivers. Note that values written to
this bit are only used when the IIC is a receiver, not a transmitter.
Writing a 1 to this bit will generate a repeated START condition on the
bus, provided it is the current bus master. This bit will always be read
as a low. Attempting a repeated start at the wrong time, if the bus is
owned by another master, will result in loss of arbitration.
For More Information On This Product,
0 = Slave Mode
1 = Master Mode
0 = Receive
1 = Transmit
0 = An acknowledge signal will be sent out to the bus at the 9th
1 = No acknowledge signal response is sent (i.e., acknowledge bit
1 = Generate repeat start cycle
0 = IIC module operates normally
1 = Halt clock generation of IIC module in WAIT mode
clock bit after receiving one byte data
= 1)
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Inter-IC Bus
IIC Register Descriptions
Technical Data
Inter-IC Bus
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