mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 382

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

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BRKDL — Breakpoint Data Register, Low Byte
18.6 Instruction Tagging
Technical Data
382
RESET:
Bit 7
Bit 7
0
6
6
0
These bits are compared to the least significant byte of the data bus or
the least significant byte of the address bus in dual address modes.
BKEN[1:0], BKDBE, BK1ALE, and BKMBL control how this byte will be
used in the breakpoint comparison.
The instruction queue and cycle-by-cycle CPU activity can be
reconstructed in real time or from trace history that was captured by a
logic analyzer. However, the reconstructed queue cannot be used to
stop the CPU at a specific instruction, because execution has already
begun by the time an operation is visible outside the MCU. A separate
instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for
tagging. The TAGLO signal shares a pin with the LSTRB signal, and the
TAGHI signal shares a pin with the BKGD signal. Tagging information is
latched on the falling edge of ECLK.
Table 18-12
operate independently - the state of one pin does not affect the function
of the other. The presence of logic level zero on either pin at the fall of
ECLK performs the indicated function. Tagging is allowed in all modes.
Tagging is disabled when BDM becomes active and BDM serial
commands are not processed while tagging is active.
Freescale Semiconductor, Inc.
For More Information On This Product,
5
5
0
Go to: www.freescale.com
shows the functions of the two tagging pins. The pins
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4
4
0
3
3
0
2
2
0
MC68HC912DG128 — Rev 3.0
1
1
0
Bit 0
Bit 0
0
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