mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 369

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

18.4.5.2 INSTRUCTION - Hardware Instruction Decode
INSTRUCTION — BDM Instruction Register (hardware command explanation)
MC68HC912DG128 — Rev 3.0
MOTOROLA
RESET:
BIT 7
H/F
0
DATA
6
0
The INSTRUCTION register is written by the BDM hardware as a result
of serial data shifted in on the BKGD pin. It is readable and writable in
Special Peripheral mode on the parallel bus. It is discussed here for two
conditions: when a hardware command is executed and when a
firmware command is executed.
Read and write: all modes
The hardware clears the INSTRUCTION register if 512 BCLK cycles
occur between falling edges from the host.
The bits in the BDM instruction register have the following meanings
when a hardware command is executed.
H/F — Hardware/Firmware Flag
DATA — Data Flag - Shows that data accompanies the command.
R/W — Read/Write Flag
BKGND — Hardware request to enter active background mode
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Firmware command
1 = Hardware command
0 = No data
1 = Data follows the command
0 = Write
1 = Read
0 = Not a hardware background command
1 = Hardware background command (INSTRUCTION = $90)
R/W
5
0
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Development Support
BKGND
4
0
W/B
3
0
BD/U
2
0
1
0
0
Background Debug Mode
Development Support
BIT 0
0
0
Technical Data
$FF00
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