mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 176

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Functions
Technical Data
176
PLLON — Phase Lock Loop On
AUTO — Automatic Bandwidth Control
ACQ — Not in Acquisition
PSTP — Pseudo-STOP Enable
Freescale Semiconductor, Inc.
Cannot be cleared when BCSP = 1 (PLL selected as bus clock).
Forced to 0 when VDDPLL is at VSS level. In limp-home mode, the
output of PLLON is forced to 1, but the PLLON bit reads the latched
value.
Automatic bandwidth control selects either the high bandwidth
(acquisition) mode or the low bandwidth (tracking) mode depending
on how close to the desired frequency the VCO is running. See
Electrical
If AUTO = 1 (ACQ is Read Only)
If AUTO = 0
In Pseudo-STOP mode, the oscillator is still running while the MCU is
maintained in STOP mode. This allows for a faster STOP recovery
and reduces the mechanical stress and aging of the resonator in case
frequent STOP conditions at the expense of a slightly increased
power consumption.
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0 = Turns the PLL off.
1 = Turns on the phase lock loop circuit. If AUTO is set, the PLL will
0 = Automatic Mode Control is disabled and the PLL is under
1 = Automatic Mode Control is enabled. ACQ bit is read only.
0 = PLL VCO is not within the desired tolerance of the target
1 = After the phase lock loop circuit is turned on, indicates the PLL
0 = High bandwidth PLL loop selected
1 = Low bandwidth PLL loop selected
0 = Pseudo-STOP oscillator mode is disabled
1 = Pseudo-STOP oscillator mode is enabled
lock automatically.
software control, using ACQ bit.
frequency. The loop filter is in high bandwidth, acquisition
mode.
VCO is within the desired tolerance of the target frequency.
The loop filter is in low bandwidth, tracking mode.
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Specifications.
Clock Functions
MC68HC912DG128 — Rev 3.0
MOTOROLA