mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 322

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MSCAN Controller
17.6 Interrupts
Technical Data
322
three bits in the identifier acceptance control register (see
Identifier Acceptance Control Register
flags (IDHIT2–0) clearly identify the filter section that caused the
acceptance. They simplify the application software’s task to identify the
cause of the receiver interrupt. In case that more than one hit occurs (two
or more filters match) the lower hit has priority.
A hit will also cause a receiver interrupt if enabled.
The msCAN12 supports four interrupt vectors mapped onto eleven
different interrupt sources, any of which can be individually masked (for
details see
Transmitter Control Register
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Transmit interrupt: At least one of the three transmit buffers is
empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXE flags of the empty message buffers are
set.
Receive interrupt: A message has been successfully received and
loaded into the foreground receive buffer. This interrupt is
generated immediately after receiving the EOF symbol. The RXF
flag is set.
Wake-up interrupt: An activity on the CAN bus occurred during
msCAN12 internal SLEEP mode.
Error interrupt: An overrun, error or warning condition occurred.
The receiver flag register (CRFLG) indicates one of the following
conditions:
– Overrun: an overrun condition as described in
– Receiver warning: the receive error counter has reached the
– Transmitter warning: the transmit error counter has reached
Structures
CPU warning limit of 96.
the CPU warning limit of 96.
msCAN12 Receiver Flag Register (CRFLG)
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MSCAN Controller
has occurred.
(CTCR)):
(CIDAC)). These identifier hit
MC68HC912DG128 — Rev 3.0
to
Receive
msCAN12
msCAN12
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