mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 233

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MCCTL — 16-Bit Modulus Down-Counter Control Register
MC68HC912DG128 — Rev 3.0
MOTOROLA
RESET:
MCZI
BIT 7
NOTE:
0
MODMC
6
0
in PBCTL, $B0) the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in
PBFLG ($B1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Read: any time
Write: any time
MCZI — Modulus Counter Underflow Interrupt Enable
MODMC — Modulus Mode Enable
For proper operation, the MCEN bit should be cleared before modifying
the MODMC bit in order to reset the modulus counter to $FF.
RDMCL — Read Modulus Down-Counter Load
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Modulus counter interrupt is disabled.
1 = Modulus counter interrupt is enabled.
0 = The counter counts once from the value written to it and will
1 = Modulus mode is enabled. When the counter reaches $0000,
0 = Reads of the modulus count register will return the present
1 = Reads of the modulus count register will return the contents of
RDMCL
5
0
stop at $0000.
the counter is loaded with the latest value written to the
modulus count register.
value of the count register.
the load register.
Go to: www.freescale.com
Enhanced Capture Timer
ICLAT
4
0
FLMC
3
0
MCEN
2
0
MCPR1
1
0
Enhanced Capture Timer
MCPR0
BIT 0
0
Timer Registers
Technical Data
$00A6
233