mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 187

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

COPCTL — COP Control Register
MC68HC912DG128 — Rev 3.0
MOTOROLA
RESET:
RESET:
CME
Bit 7
NOTE:
0/1
0/1
FCME
6
0
0
CME — Clock Monitor Enable
The VDDPLL-dependent reset operation is not implemented on first
pass products.
In this case the state of CME on reset is 0.
FCME — Force Clock Monitor Enable
Freescale Semiconductor, Inc.
Read and write anytime.
If FCME is set, this bit has no meaning nor effect.
On reset
Write once in normal modes, anytime in special modes. Read
anytime.
In normal modes, when this bit is set, the clock monitor function
cannot be disabled until a reset occurs.
See
For More Information On This Product,
0 = Clock monitor is disabled. Slow clocks and stop instruction may
1 = Slow or stopped clocks (including the stop instruction) will
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks will cause a clock reset sequence or
FCMCOP
Limp-Home and Fast STOP Recovery
5
0
0
be used.
cause a clock reset sequence or limp-home mode. See
Home and Fast STOP Recovery
CME is 1 if VDDPLL is high
CME is 0 if VDDPLL is low.
limp-home mode.
Go to: www.freescale.com
WCOP
Clock Functions
4
0
0
DISR
3
0
1
CR2
2
1
1
modes.
CR1
modes.
1
1
1
Clock Function Registers
Bit 0
CR0
1
1
Clock Functions
Technical Data
Normal
Special
Limp-
$0016
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