mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 240

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Capture Timer
Technical Data
240
PACMX — 8-Bit Pulse Accumulators Maximum Count
BUFEN — IC Buffer Enable
LATQ — Input Control Latch or Queue Mode Enable
Freescale Semiconductor, Inc.
The BUFEN control bit should be set in order to enable the IC and
pulse accumulators holding registers. Otherwise LATQ latching
modes are disabled.
Write one into ICLAT bit in MCCTL ($A6), when LATQ and BUFEN
are set will produce latching of input capture and pulse accumulators
registers into their holding registers.
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0 = Normal operation. When the 8-bit pulse accumulator has
1 = When the 8-bit pulse accumulator has reached the value $FF,
0 = Input Capture and pulse accumulator holding registers are
1 = Input Capture and pulse accumulator holding registers are
0 = Queue Mode of Input Capture is enabled.
1 = Latch Mode is enabled. Latching function occurs when
reached the value $FF, with the next active edge, it will be
incremented to $00.
it will not be incremented further. The value $FF indicates a
count of 255 or more.
disabled.
enabled. The latching mode is defined by LATQ control bit.
Write one into ICLAT bit in MCCTL ($A6), when LATQ is set
will produce latching of input capture and pulse accumulators
registers into their holding registers.
The main timer value is memorized in the IC register by a valid
input pin transition.
With a new occurrence of a capture, the value of the IC register
will be transferred to its holding register and the IC register
memorizes the new timer value.
modulus down-counter reaches zero or a zero is written into
the count register MCCNT (see
With a latching event the contents of IC registers and 8-bit
pulse accumulators are transferred to their holding registers.
8-bit pulse accumulators are cleared.
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Enhanced Capture Timer
Buffered IC
MC68HC912DG128 — Rev 3.0
Channels).
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