mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 342

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MSCAN Controller
17.13.5 msCAN12 Bus Timing Register 1 (CBTR1)
Technical Data
342
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1
Transmit point
CBTR1
Sample point
SYNC_SEG
$0103
RESET
0
0
0
0
1
.
.
W
R
0
0
0
0
1
.
.
SAMP
System expects transitions to occur on the bus during this period.
A node in transmit mode will transfer a new value to the CAN bus at this point.
A node in receive mode will sample the bus at this point. If the three samples per bit option is
Bit 7
selected then this point marks the position of the third sample.
0
0
0
1
1
1
.
.
SAMP — Sampling
TSEG22 – TSEG10 — Time Segment
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are
programmable as shown in
1. In this case, PHASE_SEG1 must be at least two time quanta.
TSEG22
Freescale Semiconductor, Inc.
This bit determines the number of samples of the serial bus to be
taken per bit time. If set three samples per bit are taken, the regular
one (sample point) and two preceding samples, using a majority rule.
For higher bit rates SAMP should be cleared, which means that only
one sample will be taken per bit.
Time segments within the bit time fix the number of clock cycles per
bit time, and the location of the sample point.
6
0
For More Information On This Product,
0 = One sample per bit.
1 = Three samples per bit
0
1
0
1
1
.
.
Table 17-6. Time segment syntax
Table 17-7. Time segment values
16 Tq clock cycles
TSEG21
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
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5
0
MSCAN Controller
.
.
TSEG20
4
0
Table
TSEG22 TSEG21 TSEG20 Time segment 2
(1)
TSEG13
0
0
1
.
.
.
17-7.
3
0
0
0
1
.
.
TSEG12
MC68HC912DG128 — Rev 3.0
2
0
0
1
1
.
.
TSEG11
1
0
2 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycle
MOTOROLA
.
.
TSEG10
Bit 0
0