mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 141

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

9.7.3 COP Reset
9.7.4 Clock Monitor Reset
MC68HC912DG128 — Rev 3.0
MOTOROLA
To prevent a COP reset from being detected during an external reset,
hold the reset pin low for at least 32 cycles. To prevent a or clock monitor
reset from being detected during an external reset, hold the reset pin low
for at least 4096 + 32 cycles. An external RC power-up delay circuit on
the reset pin is not recommended as circuit charge time can cause the
MCU to misinterpret the type of reset that has occurred.
The MCU includes a computer operating properly (COP) system to help
protect against software failures. When COP is enabled, software must
write $55 and $AA (in this order) to the COPRST register in order to keep
a watchdog timer from timing out. Other instructions may be executed
between these writes. A write of any value other than $55 or $AA or
software failing to execute the sequence properly causes a COP reset to
occur. In addition, windowed COP operation can be selected. In this
mode, a write to the COPRST register must occur in the last 25% of the
selected period. A premature write will also reset the part.
If clock frequency falls below a predetermined limit when the clock
monitor is enabled, a reset occurs.
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Resets and Interrupts
Resets and Interrupts
Technical Data
Resets
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