mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 230

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Enhanced Capture Timer
Technical Data
230
PAMOD — Pulse Accumulator Mode
PEDGE — Pulse Accumulator Edge Control
CLK1, CLK0 — Clock Select Bits
Freescale Semiconductor, Inc.
For PAMOD bit = 0 (event counter mode).
For PAMOD bit = 1 (gated time accumulation mode).
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
since the E 64 clock is generated by the timer prescaler.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock
from the timer is always used as an input clock to the timer counter.
The change from one selected clock to the other happens
immediately after these bits are written.
For More Information On This Product,
0 = event counter mode
1 = gated time accumulation mode
0 = falling edges on PT7 pin cause the count to be incremented
1 = rising edges on PT7 pin cause the count to be incremented
0 = PT7 input pin high enables M divided by 64 clock to Pulse
1 = PT7 input pin low enables M divided by 64 clock to Pulse
CLK1
PAMOD
0
0
1
1
Accumulator and the trailing falling edge on PT7 sets the PAIF
flag.
Accumulator and the trailing rising edge on PT7 sets the PAIF
flag.
0
0
1
1
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Enhanced Capture Timer
CLK0
PEDGE
0
1
0
1
0
1
0
1
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock
frequency
Falling edge
Rising edge
Div. by 64 clock enabled with pin high level
Div. by 64 clock enabled with pin low level
Clock Source
Pin Action
MC68HC912DG128 — Rev 3.0
MOTOROLA