HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 79

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

32 bit processors can either write data with byte, word or double word access. Only 8 bit are used for
address decoding. Thus the address on lines AD31 . . . AD8 are ignored.
A double word write is shown in Figure 2.18. FIFO write access have 8 bit, 16 bit or 32 bit width
alternatively. The 32 bit processor must support byte access because all other register write accesses
must have a width of 8 bit.
/BE3 . . . /BE0 control the bus lines AD31 . . . AD0 during data phase (see Table 2.22).
Data is written with
data setup time
Address and /BE require a setup time
is
not required.
An 8 bit write access (low byte) is performed in the same way as it is done with 8 bit processors. Thus
see Figure 2.14 for the timing specification.
March 2003 (rev. A)
HFC-4S
HFC-8S
/WR+/CS
AD[31:8]
/BE[3:0]
Ø
A[7:0]
ALE
/RD
À
. If two consecutive write accesses are on the same address, multiple register address write is
Figure 2.18: Write access from 32 bit processors in mode 4 (Intel, multiplexed)
Ø
t
address
ALE
Ï Ë
byte enable
t
AS
address
of /WR
and a data hold time
t
AH
t
ALEH
·
Universal external bus interface
/CS in mode 4 (Intel, multiplexed). The HFC-4S / 8S requires a
Ø
Ë
which starts with the of ALE. The hold time of these lines
double word write access
Data Sheet
Ø
t
t
DWRS
WR
Ï À
permanently high
data
data
.
t
DWRH
t
IDLE
double word write access
t
t
WR
DWRS
data
data
Cologne
Chip
t
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DWRH