HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 164

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
164 of 273
A_ST_CTRL1 [ST]
Control register of the selected S/T interface, register 1
Before writing this array register the S/T interface must be selected by register R_ST_SEL.
0
1
2
3
4
6..5
7
Bits
0
0
0
0
0
0
0
Value
Reset
Name
V_G2_G3_EN
(reserved)
V_D_HI
V_E_IGNO
V_E_LO
(reserved)
V_B12_SWAP
S/T interface
(write only)
Data Sheet
Description
Must be ’00’.
Force G2 to G3 transition
Force automatic transition from G2 to G3
’0’ = V_SET_G2_G3 of the register
A_ST_WR_STA must be set to allow transitions
from G2 to G3
’1’ = transitions from G2 to G3 are allowed without
V_SET_G2_G3 being set
Must be ’0’.
D-channel reset
’0’ = normal operation
’1’ = D-bits are forced to ’1’
Ignore E-channel data
’0’ = normal operation
’1’ = D-channel always sends data regardless of the
received E-channel bit
Force E-channel to low
(only in NT mode)
’0’ = normal operation, E-channel bits echo
received D-channel data
’1’ = E-channel bits are forced to ’0’
Swap B-channels
’0’ = normal operation
’1’ = swap B1- and B2-channel of the S/T interface
March 2003 (rev. A)
Cologne
Chip
0x32