HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 150

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
5.2.3 Clock synchronization with several TEs connected to different CO switches
Several TEs of the HFC-4S / 8S S/T interfaces can be interconnected with different central offices.
An example of this szenario is illustrated in Figure 5.3.
Instead of the external PLL shown in Figure 5.3 the internal PLL can also be used.
The sychronization registers of Figure 5.3 are shown in detail in Figure 5.4. The window detection
block (guard window) changes it’s output signal level when the phase offset between FSC and F0 is
smaller than approximately 25 s.
The timing characteristics of two unsynchronized TEs and the signals F0IO and AF0 is shown in
Figure 5.5. In this example TE0 is synchronization source for the PLL. Thus the timing offset between
FSC0 and F0IO is 62.5 s. The figure shows one sample transmit data flow and one sample receive
data flow on TE1.
Figure 5.5 shows single samples of a transmit and a receice transmission. In transmit direction, the
transmission is done either with the
Ì
Ê
5.3 Data transmission
To transfer any data over the B-channels they have to be enabled for transmission by setting
V_B1_EN or V_B2_EN in register A_ST_CTRL0. Receive is enabled by setting V_B1_RX_EN
150 of 273
Figure 5.3: Synchronization scenario with TEs connected to unsynchronized central office switches
¼
ÁÇ
¼
_
_
Ë
Ë
½
½
depending on the phase signal (see Fig. 5.4). A receive transmission is done either on
Ê
Ø
_
¼
ÁÇ
Ì
or
Ê
Ø
S/T interface
_
Data Sheet
¼
¼
_
ÁÇ
Ë
½
Ì
Ê
¼
ÁÇ
_
Ø
_
Ë
½
¼
or with the
as well.
March 2003 (rev. A)
Ì
Cologne
Chip
Ø
_
¼