HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 186

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
186 of 273
R_PCM_MD2
PCM mode, register 2
This multi-register is selected with bitmap V_PCM_ADDR = 0xA of the register
R_PCM_MD0.
0
1
2
3
5..4
6
7
Bits
0
0
0
0
0
Value
Reset
Name
(reserved)
V_SYNC_PLL
V_SYNC_SRC
V_SYNC_OUT
(reserved)
V_ICR_FR_TIME
V_EN_PLL
PCM interface
(write only)
Data Sheet
Description
Must be ’00’.
Must be ’0’.
SYNC_O with internal PLL output
’0’ = V_SYNC_OUT is used for synchronization
’1’ = SYNC_O has a frequency of the internal PLL
output signal C4O divided by 8 (512 kHz, 1024 kHz
or 2048 kHz depending on the PCM data rate)
PCM PLL synchronization source selection
’0’ = S/T interface (see R_ST_SYNC for further
sync configuration)
’1’ = SYNC_I input 8 kHz
SYNC_O output selection
’0’ = S/T receive from the selected S/T interface in
TE mode (see R_ST_SYNC register for
synchronization source selection)
’1’ = SYNC_I is connected to SYNC_O
Increase PCM frame time
This bit is only valid if V_EN_PLL is set.
’0’ = PCM frame time is reduced as selected by the
bitmap V_PLL_ADJ of the R_PCM_MD1
register
’1’ = PCM frame time is increased as selected by
the bitmap V_PLL_ADJ of the R_PCM_MD1
register
PLL enable
’0’ = normal operation
’1’ = enable PCM PLL adjustment (can be used to
make synchronization by software if no sync
source is available)
March 2003 (rev. A)
Cologne
Chip
0x15