HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 128

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
There are up to 32 receive FIFOs and up to 32 transmit FIFOs with 64 HDLC controllers in whole.
The HDLC circuits are located on the S/T interface side of the FIFOs. Thus plain data is always
stored in the FIFOs. Automatic zero insertion is done in HDLC mode when HDLC data goes from
the FIFOs to the S/T interface or to the PCM bus (transmit FIFO operation). Automatic zero deletion
is done in HDLC mode when the HDLC data comes from the S/T interface or PCM bus (receive FIFO
operation).
There is a transmit and a receive FIFO for each B-channel and for each D-channel.
The FIFO control registers are used to select and control the FIFOs of the HFC-4S / 8S. The FIFO
register set exists for every FIFO number and receive / transmit direction. The FIFO is selected by the
FIFO select register R_FIFO.
All FIFOs are disabled after reset (hardware reset, soft reset or HFC reset). With the regis-
ter A_CON_HDLC the selected FIFO is enabled by setting at least one of V_HDLC_TRP or
V_TRP_IRQ to a value different from zero.
4.1 FIFO counters
The FIFOs are realized as ring buffers in the internal or external SRAM. They are controlled by
counters. The counter sizes depend on the setting of the FIFO sizes.
and
Each counter points to a byte position in the SRAM. On a FIFO input operation
On an output operation
After every pulse on the F0IO signal HDLC bytes are written into the S/T interface (from a transmit
FIFO) and HDLC bytes are read from the S/T interface (to a receive FIFO).
The D-channel data is processed in exactly the same way as the B-channel data, except that the D-
FIFO data rate is reduced.
Additionally there are two counters
width is 4 bit for 32 kByte SRAM and 5 bit for larger SRAMs. They form a ring buffer as
do, too.
mented when a complete frame has been read from the FIFO. If
in the FIFO.
128 of 273
½
is incremented when a complete frame has been received and stored in the FIFO.
¾
is the FIFO output counter.
¾
Table 4.2:
is incremented. If
FIFO handling and HDLC controller
RAM size
½
-counter range with different RAM sizes
128k x 8
512k x 8
32k x 8
and
Data Sheet
¾
½
for every FIFO for counting the HDLC frames. Their
0x00
0x00
0x00
ÅÁÆ
¾
the FIFO is empty.
0x0F
0x1F
0x1F
Å
½
¾
½
there is no complete frame
is the FIFO input counter
March 2003 (rev. A)
½
is incremented.
Cologne
Chip
¾
½
is incre-
and
¾