HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 124

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
(For details on bitmap V_DATA_FLOW see Fig. 3.3 and 3.4 on page 97.)
124 of 273
A_CON_HDLC [FIFO]
HDLC and connection settings of the selected FIFO
Before writing this array register the FIFO must be selected by register R_FIFO.
0
1
4..2
7..5
Bits
0
0
0
0
Value
Reset
Name
V_IFF
V_HDLC_TRP
V_TRP_IRQ
V_DATA_FLOW
(write only)
Data Sheet
Data flow
Description
Transparent mode interrupt selection
Data flow configuration
Inter frame fill
’0’ = write HDLC flags 0x7F as inter frame fill
’1’ = write all ’1’ s as inter frame fill
Note: For D-channel this bit must be ’1’.
HDLC mode / transparent mode selection
’0’ = HDLC mode
’1’ = transparent mode
Note: For D-channel this bit must be ’0’.
An interrupt is generated all ¾
[n-1:0] of the ½ - or ¾ -counter become ’1’.
0 = interrupt disabled
1 = all ¾
2 = all ¾
3 = all ¾
4 = all ¾
5 = all ¾
6 = all ¾
7 = all ¾
Note: No interrupt occurs, if the -counters do
never reach the selected values. This depends on
the
0 = FIFO ° S/T,
1 = FIFO ° PCM, FIFO
2 = FIFO
3 = FIFO ° PCM, PCM
4 = FIFO ° S/T,
5 = FIFO
6 = S/T ° PCM,
7 = S/T ° PCM,
Å
¼
¾
setting.
½¾ bytes an interrupt is generated
¾
PCM, S/T
S/T,
½¼¾ bytes an interrupt is generated
¾¼
½¾ bytes an interrupt is generated
¼
bytes an interrupt is generated
bytes an interrupt is generated
bytes an interrupt is generated
bytes an interrupt is generated
FIFO
S/T
S/T
S/T
PCM
FIFO, PCM
PCM
PCM, PCM
FIFO
S/T
FIFO
PCM
S/T
March 2003 (rev. A)
Ò
bytes when the bits
Cologne
Chip
FIFO
S/T
0xFA