HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 170

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
170 of 273
A_ST_SQ_RD [ST]
S/Q multiframe register
Before reading this array register the S/T interface must be selected byregister R_ST_SEL.
3..0
4
6..5
7
A_ST_B1_RX [ST]
Receive register for the B1-channel data
This register is read automatically by the flow controller and need not be accessed by the
user. FIFOs should be used to read data.
Before reading this array register the S/T interface must be selected byregister R_ST_SEL.
7..0
Bits
Bits
0
0
0xFF
0
0
Value
Value
Reset
Reset
V_ST_B1_RX
Name
V_ST_SQ
V_MF_RX_RDY
(reserved)
V_MF_TX_RDY
Name
S/T interface
(read only)
(read only)
Data Sheet
Description
S/Q bits
Description
B1-channel data byte
TE mode: bits [3 . . . 0] are S bits [S1,S2,S3,S4]
NT mode: bits [3 . . . 0] are Q bits [Q1,Q2,Q3,Q4]
RX multiframe ready
’1’ = a complete S or Q multiframe has been
received
Reading this register clears this bit.
TX multiframe ready
’1’ = ready to send a new S or Q multiframe.
Writing to register A_ST_SQ_WR clears this bit.
March 2003 (rev. A)
Cologne
Chip
0x3C
0x34